A very large scale integrated (VLSI) complementary metal oxide semiconductor (CMOS) chip is manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.), and material modifications (i.e., oxidations, ion implants, etc). These physical and chemical operations interact with the entire wafer. For example, if a wafer is placed into an acid bath, the entire surface of the wafer will be etched away. In order to build very small electrically active devices on the wafer, the impact of these operations has to be confined to small, well defined regions.
Lithography in the context of VLSI manufacturing CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base material is modified by a specific operation in a sequence of processing steps. The manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending with the removal of the expended photoresist to make way for the new resist to be applied for another iteration of this process sequence.
The basic lithography system consists of light source, a stencil or photo mask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. The aligning may take place in an aligning step or steps and may be carried out with an aligning apparatus. Since a wafer containing from 50 to 100 chips is patterned in steps of 1 to 4 chips at a time, these lithography tools are commonly referred to as steppers. The resolution, R of an optical projection system such as a lithography stepper is limited by parameters described in Raleigh's equation: EQU R=k .lambda./NA
Where .lambda. represents the wavelength of the light source used in the projection system and NA represents the numerical aperture of the projection optics used. k represents a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and can range from about 0.8 down to about 0.5 for standard exposure systems. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 248 nm wavelengths, but mid ultra violet (MUV) steppers with a wavelength of 356 nm are also in widespread use.
Conventional photo masks consist of chromium patterns on a quartz plate, allowing light to pass wherever the chromium has been removed from the mask. Light of a specific wavelength is projected through the mask onto the photoresist coated wafer, exposing the resist wherever hole patterns are placed on the mask. Exposing the resist to light of the appropriate wavelength causes modifications in the molecular structure of the resist polymers which allows developer to dissolve and remove the resist in the exposed areas. (Negative resist systems allow only unexposed resist to be developed away.) The photo masks, when illuminated, can be pictured as an array of individual, infinitely small light sources which can be either turned on (points in clear areas) or turned off (points covered by chome). If the amplitude of the electric field vector which describes the light radiated by these individual light sources is mapped across a cross section of the mask, a step function will be plotted reflecting the two possible states that each point on the mask can be found (light on, light off).
The conventional photo masks are commonly referred to as chrome on glass (COG) binary masks, due to the binary nature of the image amplitude. The perfectly square step function exists only in the theoretical limit of the exact mask plane. At any distance away from the mask, such as in the wafer plane, diffraction effect will cause images to exhibit a finite image slope. At small dimensions, that is, when the size and spacing of the images to be printed are small relative to the .lambda./NA, electric field vectors of adjacent images will interact and add constructively. The resulting light intensity curve between the features is not completely dark, but exhibits significant amounts of light intensity created by the interaction of adjacent features. The resolution of an exposure system is limited by the contrast of the projected image, that is, the intensity difference between adjacent light and dark features. An increase in the light intensity in nominally dark regions will eventually cause adjacent features to print as one combined structure rather than discrete images.
The quality with which small images can be replicated in lithography depends largely on the available process latitude; that is, the amount of allowable dose and focus variation that still results in correct image size. Phase shifted mask (PSM) lithography improves the lithographic process latitude or allows operation at a lower K value (see equation 1) by introducing a third parameter on the mask. The electric field vector, like any vector quantity, has a magnitude and direction, so, in addition to turning the electric field amplitude on and off, it can be turned on with a phase of about 0.degree. or turned on with a phase of about 180.degree.. This phase variation is achieved in PSMs by modifying the length that a light beam travels through the mask material. By recessing the mask to an appropriate depth, light traversing the thinner portion of the mask and light traversing the thicker portion of the masks with be 180.degree. out of phase; that is, their electric field vector will be of equal magnitude but point in exactly opposite directions so that any interaction between these light beams results in perfect cancellation. For more information on PSMs, please see "Phase-Shifting Mask Strategies: Isolated Dark Lines", Mark D. Levenson, Microlithography World, March/April 1992, pp. 6-12, the entire contents of which are hereby incorporated by reference.
Even though resolution enhancement through the use of hard phase shifted masks (frequency doubling masks) has been extensively proven, implementation of this technique is critically dependent on computer assisted (CAD) technology that can modify existing circuit designs to incorporate the additional design levels needed to build a phase shifted mask. Design modifications consist of defining regions on the mask that require phase shifting (i.e., by etching into the mask substrate) relative to the rest of the mask, and of creating shapes that are to eliminate lines printed by unwanted phase edges. The basic concept of creating a phase transition across any small feature is easily realized and can be done, given sufficient time, on a graphics terminal by hand. The challenge that needs to be met before introducing hard phase shifters to VLSI product programs lies in the rapid, reliable design modifications of complex chip designs.
Residual phase edges in a standard two phase (0.degree. and 180.degree. phases) layout have to be removed either by a phase gradient approach or by use of a trim mask. Phase gradient approaches use a significant amount of space and gravely impact layout density. Trim mask approaches require two exposures for every conventional exposure field. This is extremely costly in a manufacturing environment.
Standard alternating PSMs using only two phase regions yield asymmetric intensity profiles which can cause a skew in the image and reduction in process latitude.
Alternating PSMs using either a deposited shifter material or a quartz etch process, are very susceptible to 180.degree. phase defects which cannot be repaired with state of the art repair tools, are extremely elusive to existing inspection tools, yet have significant impact on printed wafer images.
Asymmetric frequency doubling PSMs (alternating or phase edge) are very difficult to design even when requiring only two distinct phase regions.
Compactor based design systems are only applicable to dark field PSM designs and cannot be used for the design of bright field PSMs such as the ones required for logic gate levels.
Inverse problem methods of PSM design are extremely computational intensive and have not been demonstrated to be feasible for actual chip designs.
Router based PSM design tools cannot be modified to handle the task of designing PSMs with multiple (more than two) phase regions since the premise of the router concept is to form a single phase polygon using the existing chrome designs as sides to the polygon. So the resulting mask layout can only consist of a single phase region, the mask background, and the chrome features, allowing for only two phase assignments.